The invention relates to a modulation code system as shown in FIG. 6, including an encoder 100 for transforming an original signal s into an encoded signal c satisfying predefined second constraints before being transmitted via a channel 300 or stored on a recording medium. The modulation code system further comprises a decoder 200 for decoding the encoded signal c after restoration or receipt back into the original signal s.
Such a modulation code system known in the art is substantially used in data transmission systems or data storage systems.
The invention further relates to known methods of operating the encoder 100 and the decoder 200.
Traditionally, encoders or decoders of modulation code systems use specific modulation methods, e.g. the enumerative encoding method or the integrated scrambling method. The enumerative encoding method is e.g. known from K. A. S. Immink, xe2x80x9cA practical method for approaching the channel capacity of constrained channelsxe2x80x9d, IEEE Trans. Inform. Theory, vol. IT-43, no. 5, pp. 1389-1399, September 1997. The integrated scrambling method is e.g. known from K. A. S. Immink, xe2x80x9cCodes for mass data storage systemsxe2x80x9d, Shannon Foundation Publishers, The Netherlands, 1999.
These methods allow the transformation of the original signal s into the signal c satisfying yxc complicated constraints and back, usually at a modulation code rate close to 1. The rate of a modulation code is a number that refers to the average number of encoded signals per source symbol: for example, an encoder of rate xc2xd code produces (on average) two encoded symbols for each source symbol.
At least the decoder of such known modulation code systems is usually implemented in hardware so as to allow high speed operation. However, hardware implementation of the above-mentioned modulation code methods disadvantageously requires quite a lot of hardware, e.g. to store the required tables.
Starting from the prior art, it is the object of the invention to improve a known modulation code system and known methods of operating an encoder and a decoder of said modulation code system such that they require less hardware.
This object is solved as defined in claim 1 by embodying the encoder such that it comprises a modulation code encoder for transforming the original signal s into an intermediate signal t satisfying predefined first constraints and a transformer encoder for N-times integrating said intermediate signal t in order to generate said encoded signal c and by embodying the decoder such that it comprises a transformer decoder for N-times differentiating the encoded signal c after restoration in order to regenerate said intermediate signal t and a modulation code decoder for decoding said intermediate signal t into said original signal s, N being an integer greater than 1.
The first constraints may in general be simpler, equal or more complicated than the second constraints. However, in preferred embodiments, the first constraints are usually simpler than the second constraints.
The claimed design of the modulation code system, in particular the series connection of the modulation code encoder with the transformer encoder within said encoder and the series connection of the transformer decoder with said modulation code decoder within said decoder, ensures that the hardware expense for implementing the encoder and the decoder is advantageously essentially reduced.
The object is further solved by the encoder as defined in claim 2. The above-mentioned advantage applies to said encoder as well.
An example of a simple and less expensive implementation of the encoder is defined in claim 3.
The encoder is preferably implemented in hardware in order to ensure a high operation speed.
The method is especially well-suited for a modulation code rate close to one. In that case, the modulation code encoder as well as the transformer encoder must both have a modulation code rate close to 1 because the modulation code rate of the entire encoder corresponds to the product of the modulation code rates of the modulation code encoder and the transformer encoder.
Advantageously, the modulation code encoder is a (0,k)-encoder; in that case, the intermediate signal t is (0,k)-constrained and thus the first constraints satisfy very simple constraints.
The object of the invention is further solved by an encoding method as defined in claim 7 for transforming an original signal s into an encoder signal c satisfying predefined second constraints. The advantages of said encoding method correspond to the above-mentioned advantages of the encoder.
The object of the invention is further solved by the decoder as defined in claim 8. The advantages of said decoder, namely that less hardware is required for implementing said decoder, correspond to the advantage mentioned above.
The transformer decoder represents a sliding block decoder.
The transformer decoder is preferably at least partly implemented in hardware in order to achieve a high operation speed.
In a very simple embodiment, the modulation code decoder is a (0,k)-decoder with the result that it decodes a simple (0,k)-pattern constrained intermediate signal t back into the original signal s.
Further advantageous embodiments of the invention are defined in the dependent claims.
Finally, the object of the invention is solved by the decoding method as defined in claim 13; the advantages of this method correspond to the advantages of the decoder mentioned above.